1. Field of the Invention
The present invention relates to a processing device, a method of determining an internal configuration of the processing device, and a processing system.
2. Description of the Related Art
As a means for LSI (Large Scale Integration) realizing desired application, there are ASIC (Application Specific Integrated Circuit), processors, and the like. Being hardwired, the ASIC has a drawback of low programmability. In addition, the ASIC realizes the application by the development to transistors, and therefore, in a series of operations from the start to end of application processing, efficiency in terms of effective use of resources is low.
The processors, if adopting a distributed processing architecture such as multi-processing where resources are not shared, require a compiler with a high breakdown capability for the purpose of task breakdown of application to each processor element. However, at present, such a compiler is not available, and after the task breakdown is manually performed, an enormous amount of time has to be spent for minute adjustment in order to optimize the task breakdown.
Moreover, the processors, if adopting the distributed processing architecture where resources are not shared, have a drawback that it is difficult to realize a high usage rate of the resources. Because the resources are not shared among the processors, each of the processors has to use up the limited resources. For this reason, even with the difficulty in the task breakdown and in the optimization of the task breakdown, the processors cannot be said to have full advantage in terms of processing performance and circuit area.
More specifically, in a multiprocessor, a plurality of processor cores are connected to one another via a network or a bus, and an expansion processing unit or a programmable expansion processing unit is provided exclusively for each of the processor cores. Each processor core uses resources of the expansion processing unit or programmable expansion processing unit to execute arithmetic processing. However, since the processor cores are provided with the processing resources independently, they do not always use the resources fully efficiently to deal with tasks assigned to each of them. In many cases, resource usage is not efficient such as a case where some processor cores are frequently idle, finishing the arithmetic processing in a short time while some processor cores constantly work on the arithmetic processing and cannot complete it by the time required sometimes. Such a case further increases as more importance is put on efficiency in software design (function assignment). On the contrary, loads of task breakdown and a compiler increase as more importance is put on resource usage efficiency. It is considered that it is difficult to develop such a compiler.
Under the above-described circumstances, there is a demand for an art that can easily realize desired application and realize effective use of resources. In order to meet such a demand, for example, LSI whose architecture is reconfigurable (reconfigurable LSI) is being developed.
Japanese Unexamined Patent Application Publication No. 2000-36737 discloses an art for building logic architecture using an electrically reconfigurable gate array. Japanese Unexamined Patent Application Publication No. Hei 6-231283 discloses an art in which a programmable wiring area enabling interconnection of input/output circuits or interconnection of an input/output circuit and a logic/wiring block is provided inside a programmable logic chip, whereby an increase in delay amount and an increase in wiring elements used for chip-to-chip wiring are prevented when a multi-chip system is configured.
In a processing device constituted as LSI, the speed and integration degree of a processing unit is on an increasing trend, but an external interface unit is not necessarily improved in speed as much as the processing unit. This involves a possibility that the speed and the integration degree of the processing unit are higher than necessary. This is because an operating speed (processing speed) of the processing unit may be slow, providing that it falls in a range satisfying a desired throughput (the number of times the processing device outputs processed data to an external part per unit time). That the speed and the integration degree of the processing unit are excessively high implies that there exist a large number of resources which are not used for processing (registers, operators, and so on) and thus a circuit area is uselessly large.